1. Field of the Invention
The present invention relates to a bidirectional signal transmission circuit and a bus system for facilitating impedance matching and fast signal transfer.
2. Description of the Prior Art
As MPUs and memory devices become faster, the demand for speeding up data transfer on buses is growing in recent years. However, such speedups also incur difficulties in the proper transfer of data. This is because disturbances such as reflections of signals due to a mismatch with a characteristic impedance of a transmission line and crosstalk between adjacent lines become more serious with increase in data transfer rate.
To avoid such unwanted signal reflections, impedance matching is commonly performed by means of series termination that inserts a resistor in series with a transmission line or parallel termination that inserts a resistor between a transmission line and a power or ground plane.
The series termination couples a resistor in series between an output buffer (a driver) and a transmission line, to match the output impedance with the transmission line impedance and reduce the output amplitude. When the transmission line is unidirectional, placing the resistor on the output line (i.e. at the output port or terminal) of the output buffer is effective. The unidirectional transmission line referred to here is a transmission line that transmits signals only in one direction.
FIG. 1 shows an example circuit where series termination is applied to an unidirectional transmission line. To eliminate an impedance mismatch between an output buffer 801 and a unidirectional transmission line 803 coupled thereto, a resistor 804 is positioned in series between the output buffer 801 and the unidirectional transmission line 803. Let Ro1 be the output resistance of the output buffer 801, Zo be the characteristic impedance of the unidirectional transmission line 803, and Rs1 be the value of the resistor 804. Then Rs1 is determined by the equation Rs1=Zoxe2x88x92Ro1, to match the output impedance (Rs1+Ro1) with the transmission line impedance (Zo) (i.e. to establish the relation Rs1+Ro1=Zo). Thus, the resistor 804 serves to match the impedance of the output buffer side (output impedance) to that of the unidirectional transmission line side at a junction between the resistor 804 and the transmission line 803.
However, the above series termination is not applicable to a bidirectional transmission line that transmits signals in two directions, because in the case of the bidirectional transmission line its both ends will act as output ends as well as input ends.
FIG. 2 shows an example circuit where a resistor is series-connected to one end of a bidirectional transmission line. Suppose Rs1 of a resistor 906 is determined in the same way as FIG. 1. When transmitting a signal from an output buffer 901, an output impedance and an impedance of a bidirectional transmission line 905 match. However, when transmitting a signal from an output buffer 903, an impedance mismatch occurs due to the absence of a series terminating resistor between the output buffer 903 and the bidirectional transmission line. 905, as a result of which signal reflections arise.
Several impedance matching methods for bidirectional transmission lines have been devised in recent years through the use of various bus topologies and termination techniques. Examples of such methods are RSL (Rambus Signaling Logic) proposed by Rambus, Inc. and SSTL (Stub Series Terminated Logic) [EIAJED-5512] standardized by the Electronic Industries Association of Japan. FIGS. 3 and 4 show example circuits that employ RSL and SSTL, respectively. In the figures, a portion enclosed by a dashed line shows a pair of an output buffer (a driver) and an input buffer (a receiver) in greater detail. The output buffer in FIG. 3 is an open drain output, whereas the output buffer in FIG. 4 is a tri-state output.
RSL in FIG. 3 is characterized by a restricted bus topology where single-stroke configuration with no branch lines is adopted to a bus line, in order to ensure impedance matching. In SSTL in FIG. 4, on the other hand, a bus line is parallel terminated and series terminating resistors are arranged at branch points of lines branched from the bus line, to match the branch lines to the bus line. Thus, SSTL enables impedance matching for a bus topology that has branch lines.
However, with conventional bus interfaces, it is becoming increasingly difficult to improve clock frequencies for faster signal transmission and at the same time ensure impedance matching.
In the case of RSL in FIG. 3, when mounting an LSI (Large-Scale Integration) onto a board, leads included in the LSI package will end up being branch lines, so that it is impossible to form a bus line of single-stroke configuration which contains no branch lines. Though such a bus line can operate without problems within a frequency range up to the order of some hundreds of megahertz, at higher frequencies (the order of gigahertz) the bus line inevitably suffers signal reflections because of the presence of several branch lines (leads) which do not match with the bus line.
In the case of SSTL in FIG. 4, the series terminating resistors arranged at the branch points serve to match impedances when signals are transmitted from the branch lines to the bus line (output onto the bus line) but not when signals are transmitted from the bus line to the branch lines (input from the bus line). Therefore, such a bus line also suffers signal reflections at high frequencies (the order of gigahertz).
The first object of the invention is to provide a bidirectional signal transmission circuit that ensures impedance matching and fast signal transmission without restrictions on bus topology, regardless of in which direction a signal is to be transmitted.
The second object of the invention is to provide a bus system that facilitates impedance matching and fast signal transmission.
The third object of the invention is to provide a bus interface that delivers high noise immunity in addition to the above stated effects.
The first and second objects can be fulfilled by a bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line, including: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.
With the above construction, the impedance on the side of the transceiver varies from the time of signal transmission by the transceiver to the time of signal reception by the transceiver. Accordingly, the transceiver and the bidirectional transmission line can easily be matched regardless of whether the transceiver transmits or receives a signal, and the signal transfer can be accelerated.
Here, a combined impedance of an output impedance of the transceiver and the impedance of the first element may match a characteristic impedance of the bidirectional transmission line.
Here, the first element may be a resistor.
With the above construction, the first element with the proper impedance can easily be realized by means of a resistor, and the second element can easily be realized by means of a wire or a pattern on a printed board.
Here, the first element may be a driver that amplifies an output current of the transceiver.
With the above construction, the impedance matching is ensured by matching the transceiver to the bidirectional transmission line or by matching the bidirectional transmission line to the transceiver. Further, even when the current drive ability of the transceiver is low, such a drive ability is appropriately adjusted by equipping with a driver that has a drive ability responsive to the load on the bidirectional transmission line.
Here, the first element may be a combination of a resistor and a driver that amplifies an output current of the transceiver.
With the above construction, not only the stated effect due to the driver can be achieved but also the proper impedance of the first element can be attained by the resistor.
Here, the switching unit may have a first switching element and a second switching element which inversely toggle between an on state and an off state, wherein the first switching element and the first element are connected in series to form a first series circuit, the second switching element and the second element are connected in series to form a second series circuit, and the first series circuit and the second series circuit are connected in parallel between the transceiver and the bidirectional transmission line.
With the above construction, the first or second element is coupled to either the transceiver or the bidirectional transmission line via the first or second switching element. The first and second switching elements can be implemented at low cost by, for instance, FET switches.
Here, the switching unit may have a first switching element and a second switching element which inversely toggle between an on state and an off state and a third switching element and a fourth switching element which inversely toggle between the on state and the off state, wherein the first switching element and the third switching element simultaneously toggle into a same state, the first switching element, the first element, and the third switching element are connected in series in the stated order, to form a first series circuit, the second switching element, the second element, and the fourth switching element are connected in series in the stated order, to form a second series circuit, and the first series circuit and the second series circuit are connected in parallel between the transceiver and the bidirectional transmission line.
With the above construction, the first or second element is coupled between the transceiver and the bidirectional transmission line through switching elements connected to both sides of the first or second element. Accordingly, when no connection is required, the first and second elements are completely discoupled from the transceiver and the bidirectional transmission line, with it being possible to eliminate any isolated line portions which are not electrically terminated.
Here, the first switching element and the second switching element may inversely toggle in response to one of a write signal and an output enable signal given to the transceiver.
With the above construction, the first and second switching elements inversely toggle in response to a write signal or an output enable signal, so that the connection state can be switched between the first element and the second element with the input/output timing of the transceiver.
The second object can also be fulfilled by a bus system for transmitting an address and data between a first LSI (Large Scale Integrated Circuit) that performs an access and a second LSI that is to be accessed, including: a first unidirectional bus for transmitting an address and data outputted from the first LSI, to the second LSI; and a second unidirectional bus for transmitting data outputted from the second LSI, to the first LSI, wherein when the first LSI performs a write access, a write address and write data are transmitted through the first unidirectional bus, and when the first LSI performs a read access, a read address is transmitted through the first unidirectional bus and read data is transmitted through the second unidirectional bus.
With the above construction, the write access and the read access from the first LSI to the second LSI are carried out using only unidirectional buses, so that impedance matches are easily attained.
Here, signal lines included in the first unidirectional bus and signal lines included in the second unidirectional bus may be alternately routed.
The third object can be fulfilled with this construction. That is to say, by alternately routing the signal lines included in the first unidirectional bus with the signal lines included in the second unidirectional bus, interference such as crosstalk is suppressed and noise immunity is improved.
Here, in at least one of the first LSI and the second LSI, input and output terminals that correspond to the alternately routed signal lines may be alternately placed.
With the above construction, the input terminals and the output terminals are alternately arranged in the LSI, which further benefits the noise immunity.
Here, in the write access the write data may be transmitted through the first unidirectional bus after the write address.
With the above construction, the write address and the write data are time division multiplexed on the first unidirectional bus, so that the number of terminals to be mounted in the first and second LSIs can be minimized.
Here, the bus system may further include a maintaining unit for maintaining, while at least one of the first unidirectional bus and the second unidirectional bus is idle, a potential of the idle bus at a fixed level which is one of a low level and a high level.
With the above construction, the potential of the bus that is being idle is held at the fixed level, which further benefits the noise immunity.
Here, the maintaining unit may maintain the potential of the idle bus at the fixed level at both ends of the idle bus.
With the above construction, the potential of the bus that is being idle is held at the fixed level at both ends of the bus, so that the time taken for attaining the fixed potential across the bus is shortened and the transmission speed is increased.